Give your gizmo the gift of sight
Following discussions from a previous post in another forum, I’m writing a three-part blog post on chip design, as I experience it professionally, and how I see it relating to both the open source community and the DIY crowd. This first post will discuss the chip design process itself. I am going to focus on what could be called “indie chip design” as it may be executed by a small company or even a single person. Obviously I can’t explain how to design the next hot microcontroller in a single blog post, but you should get a flavor for how this process is similar to and different from, say, designing a printed circuit board (PCB).
First a little background- I work in a small company Centeye that makes image sensor chips for various embedded vision and robotic applications. These designs incorporate both digital and analog circuitry, including pixel circuits, on the same chip. Due to our size (and budget!) we favor a minimalist approach to these image sensors. The chips themselves typically have anywhere from a thousand to at most several million transistors and are simple enough in architecture that one person (e.g. me) can handle the whole design. Our chips are three to six orders of magnitude simpler (by transistor count) than a contemporary processor or GPU chip, which currently contain up to several billion transistors.
The “complexity” of any design is an important consideration. Consider how much the complexity of a PCB can vary. At one end you have a 10-plus layer state-of-the-art computer motherboard. At the other end you can have a single layer PCB that uses a basic Atmel and a few discrete parts to blink an LED. Both of these are “circuit boards”, but one can be designed by a single person in a fraction of an hour while the other requires specialized (e.g. expensive) software and a team of engineers putting in person-years of effort. The design methodologies are certainly different for each board- You can take a cowboy approach and “wing it” when designing the blinking LED board. But the computer motherboard requires careful and rigorous preliminary research, planning, and coordination between the designers. Now I don’t want to imply that I design chips with a cowboy approach (well not usually) but the simplicity of our designs allows for different methodologies than what are needed for, say, designing a new GPU.
The PCB design process
As a starting point, that more people here would be familiar with, let’s first consider the PCB design process that one might follow if using a set of tools like Eagle. You might follow these steps:
Specification: Decide what you want to make. Decide some basic components to include (e.g. what processor to use or other desired components). Decide the interface, for example how you power and “talk to” the board if there is an I/O aspect.
Sketching and Research: Sketch out different sections of the board schematic (on paper or with Eagle), read datasheets, and determine what exact components you need. (For example- what voltage regulators do you need, what caps / resistors do those regulators need, and so on.)
Schematic Entry: Enter the schematic diagram.
Board Layout: Place components in desired locations, and then route, route, route to make all the desired electrical connections between them.
Verification: Run design rule checks. You need to verify, for example, that routed wires are thick enough, that unconnected wires are not too close together, and that no routing is too close to the board's edge or to holes. Run electrical rule checks to make sure that you didn’t accidentally connect two nodes that should be separate.
Fabricate: Generate the Gerbers and get the board made.
Populate: Solder components to the board. When done, power it up and test it.
Depending on the board, you may do some of the above steps in parallel and/or repeat earlier steps if you find some problem with the design, for example if the components don’t fit in a desired space.
Chip layout vs. PCB layout
The most fundamental way that chip design is different from PCB design is in the purpose of the layout. For PCBs, the "layers" of the layout define the electrical connections between the different components that will be soldered to the board. Some layers define etched copper patterns to form "wires", while other layers define “vias” for electrical contact between layers.
For an example of chip layout, look at the photo on the top of this post for details. On a chip layout, some layers are similarly used to form such electrical connections. Generally these are the “metal” layers with a low resistance, and are often made on the actual chip with aluminum or copper. This appears as "blue" in the above layout. There are also “via” and “contact” layers defining similar connections between layers, visible above as black squares.
However there are other layers that are used to actually form devices when geometric objects are drawn according to well-defined rules. When designing a chip, you not only draw the wiring between transistors, capacitors, and resistors, but you also draw those transistors, capacitors, and resistors themselves.
For example, there is one red layer called “polysilicon” which is a conductor but generally has a higher resistance. If you draw a long, thin wire of polysilicon, you get a resistor. (A long thin wire of metal also gives you a resistor but of much less resistance.) To form a capacitor, you can draw two plates of polysilicon on top of each other, with one plate located on “polysilicon 1” (light red) which is deeper in the chip and the other plate located higher up on “polysilicon 2 (dark red)”. They will be separated by a thin insulator, so that the two plates and insulator form a capacitor. A transistor (such as a MOSFET) can be formed by crossing a polysilicon wire over a box of “active” layer (green). I won’t describe all the possibilities- that could fill a textbooks- but hopefully you get the basic idea.
In other words, the fundamental difference is that on a PCB, the geometric figures you draw define the electrical connections between components, while on a chip, the geometric figures also create the components themselves.
As you can imagine, the “design rule checks” for chips are much more complicated. Fortunately all that is now automated.
A chip design generally uses a hierarchical structure based on what we call “cells”. A basic cell may be an OR gate, a single capacitor, or a single pixel circuit. Then we can create higher level cells by “instancing” and connecting together existing lower level cells, and optionally adding new layout. For example, a pixel cell may contain a couple transistors and a photodiode, and routing for power line and output. Then a pixel array cell can be constructed from a large 2D array of individual pixel cells. Similarly a flip flop cell can be constructed from a few gates, and a register cell can be constructed from an array of flip flop cells. The “top level cell” would be the whole chip.
This hierarchical structure is analogous to the hierarchical structure of a computer program. You have variables and individual instructions at the bottom level, then lower level functions that use these variables and instructions, higher level functions that call these lower level functions, and finally the “main” function at the top.
In a chip design, the cell structure is present in both the schematic level and the layout. Consider a pixel cell: In the schematic entry software I use, elementary cells like “capacitor”, “resistor”, and “N-type transistor” are already defined. The pictures below show examples. To make a pixel cell I would instance the appropriate components (generally some transistors and a photodiode), draw wires to connect them, and create a “symbol” that represents the pixel cell. Then I would create an associated layout for the cell. This would be a drawing of the different layers (metal, polysilicon, active layer, etc.) that together create the electronic circuitry depicted in the schematic.
Once I have created a cell, I would next “verify” it. This includes running design rule checks such as making sure wires are thick enough and that unconnected wires are not too close (sound familiar?). This also includes other more esoteric design rule checks such as making sure the different layers are properly drawn to form devices like transistors and capacitors. I also run a “layout vs schematic” test to make sure that both the schematic and layout versions of the cell show the same circuit. If needed, I may also perform a circuit simulation (using SPICE) to verify that the circuit should function as I intend. In the SPICE simulation I would present different inputs to the circuit and verify that the simulated output is as expected. For example for a NOT gate I would apply a digital 0 and then 1 and verify that the output was the opposite. I would also verify that the threshold voltage (the crossover from 0 to 1) is appropriate.
Once a cell has been completed, I can then construct and verify higher level cells in the same manner. For example I could create a pixel array by instancing individual pixel cells. I would verify the pixel array cell and move on to the next cells until the chip is finished.
One nice thing about the cell architecture is that once a cell is made, you can reuse it in other chip designs, either verbatim or with some changes. This is much like how you can re-use existing source code to write a new program. Also it is possible to acquire libraries of cells for many common circuits- I never design my own flip flop cells- I used existing flip flop cells that either the CAD tool company or the chip foundry has provided- I not only save time but have the peace of mind of using a cell that I know works.
This ability to reuse cell designs is crucial for reducing design time. My record for designing a chip, start to finish, is three hours sitting in a Dupont Circle coffee house in DC back in 2001. All of the cells were reused, with one or two modified, except for the top level cell which was constructed from scratch. (Yes, that chip did work!)
The three pictures below show sample layout and schematic of pixel cells.
Above: Layout of a single pixel cell. "blue" is the lowest metal layer e.g. metal1, "grey" is the second metal layer e.g. metal2, tan is the third metal layer e.g. metal3. White squares are "vias" between metal layers. The big area with right-hand cross hatches is the "N" side of the photodiode. The "P" side is the chip substrate itself.
Above: Schematic diagram of a single pixel circuit. Node "rowsel" is used to select a row of pixels. Node "out" is the column output. Nodes "prsupply" and "swvdd" are effectively power supplies for the pixel.
Above: 16x16 array of single pixel circuits used to form a 16x16 focal plane array section.
The Indie chip design process:
Now I can summarize the process I use to design a new image sensor chip:
Specification: Typically I would hand draw a few critical items in my notebook. This may be the schematic diagram for individual pixel circuits or related subcircuits. This would also include a specification of the interface, such as how I want the digital signals provided to the chip to control the chip, and the nature of the output (analog, digital, etc.)
Sketching and Research: Next I would sketch out a cell hierarchy for the chip, including initial hand-drawn schematic sketches for the most critical cells and how they interact. I would also look through existing designs and libraries for cells that I can reuse and/or modify.
Design the chip, cell by cell: Next I would go through the process of designing the cells that will make up the chip design. I would start out with the basic cells, construct both layout and corresponding schematic and symbols, and do any verification. Generally I would both create and verify a given cell before moving up the hierarchy.
Redesign: Sometimes it just happens that through the process of designing it you realize that something may not work or fit. In this case you just have to go back and change some aspect of the design.
Padframe: The padframe is a cell that contains all the “pads” which are the electrical contacts between the chip and the outside world.
Top level cell: I would then assemble and verify the top level cell of the chip.
Tape-out and Fab: The term “tape-out” is the chip design equivalent to making Gerber files for a PCB. I think this is an archaic term that comes from a time when the layout files were literally written to magnetic tape that was then mailed out to the fab company. Nowadays of course you just create the layout file and email it in.
Dicing and Packaging: The chips come back in wafers (see this previous post). We send them out to a company to dice them e.g. cut them up into individual dies. Packaging refers to the process of connecting the individual dies to some sort of package that allows you to solder them to a board. You can’t solder directly to the chip (the pads are between 60 and 100 microns wide!) so typically one uses a wire bonding machine to connect the chip to a package with 1-mil thick gold wire. We own a wire bonding machine so we just wire bond the chips directly to a test PC board, in a process described here. Once this is done we can then test the chip to verify it works.
Cost? For a single chip design I’ve spent anywhere from $980 to $58k to get multiple (between 4 and 40) copies of a single chip design made. For wafers I’ve spent anywhere from about $18k to just under $100k to get multiple wafers containing multiple chip designs made, generally yielding four to eight thousand chips. (Note that for a fine-scale digital process used to make current GPUs or CPUs, you can probably spend millions.) As you make more the price drops further. The economies of scale are drastic. I will comment on that in another post.
Time? You can get PCBs made the same day if you really need it. For chips I wait anywhere from 6 weeks to 4 months. Yes, the long wait can make one nervous…
Simplicity and avoiding feature creep
A final thought on the chip design process as I experience it- Simplicity rules! The final part of verifying a chip design is stressful since you really can’t fully verify the chip design, including how the individual cells interact, until you actually fabricate the chip. (Actually for digital circuits the behavior is generally predictable if you use the right practices, but analog circuits are more complicated.) The best I can do until then is to rely on circuit simulations of a limited set of scenarios, along with double, triple, and quadruple checking, and hope that the resulting design works.
So as a result of this, I’ve found that the best habit to have is to be very choosy about what features to include and keep all aspects of the chip (interface, layout, topology, etc.) as simple as possible. The simpler the chip, the easier the layout and the verification, and the less opportunity you have to screw things up! The 80/20 principle is key here- Only include what is necessary. This can be a challenge because we engineers are notorious for saying “hey we can add this feature, and while we’re at it add that one and this other one too”.
In my next post, I'll discuss issues the real issues I face when trying to "open" up chip designs, and how these may be addressed.